Specification Update

R
30 Mobile Intel® Celeron® Processor Specification Update
M12.
BTMs May Be Corrupted During Simultaneous L1 Cache Line Replacement
Problem: When Branch Trace Messages (BTMs) are enabled and such a message is generated, the BTM may be
corrupted when issued to the bus by the L1 cache if a new line of data is brought into the L1 data cache
simultaneously. Though the new line being stored in the L1 cache is stored correctly, and no corruption
occurs in the data, the information in the BTM may be incorrect due to the internal collision of the data
line and the BTM.
Implication: Although BTMs may not be entirely reliable due to this erratum, the conditions necessary for this
boundary condition to occur have only been exhibited during focused simulation testing. Intel has
currently not observed this erratum in a system level validation environment.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M13.
Near CALL to ESP Creates Unexpected EIP Address
Problem: As documented, the CALL instruction saves procedure linking information in the procedure stack and
jumps to the called procedure specified with the destination (target) operand. The target operand
specifies the address of the first instruction in the called procedure. This operand can be an immediate
value, a general purpose register, or a memory location. When accessing an absolute address indirectly
using the stack pointer (ESP) as a base register, the base value used is the value in the ESP register
before the instruction executes. However, when accessing an absolute address directly using ESP as the
base register, the base value used is the value of ESP after the return value is pushed on the stack, not the
value in the ESP register before the instruction executed.
Implication: Due to this erratum, the processor may transfer control to an unintended address. Results are
unpredictable, depending on the particular application, and can range from no effect to the unexpected
termination of the application due to an exception. Intel has observed this erratum only in a focused
testing environment. Intel has not observed any commercially available operating system, application, or
compiler that makes use of or generates this instruction.
Workaround: If the other seven general purpose registers are unavailable for use, and it is necessary to do a CALL via
the ESP register, first push ESP onto the stack, then perform an indirect call using ESP (e.g., CALL
[ESP]). The saved version of ESP should be popped off the stack after the call returns.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M14.
Memory Type Undefined for Non-memory Operations
Problem: The Memory Type field for nonmemory transactions such as I/O and Special Cycles are undefined.
Although the Memory Type attribute for nonmemory operations logically should (and usually does)
manifest itself as UC, this feature is not designed into the implementation and is therefore inconsistent.
Implication: Bus agents may decode a non-UC memory type for nonmemory bus transactions.
Workaround: Bus agents must consider transaction type to determine the validity of the Memory Type field for a
transaction.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.