Specification Update

Mobile Intel® Celeron® Processor Specification Update 31

M15.

FP Data Operand Pointer May Not Be Zero After Power On or Reset

Problem: The FP Data Operand Pointer, as specified, should be reset to zero upon power on or Reset by the

processor. Due to this erratum, the FP Data Operand Pointer may be nonzero after power on or Reset.

Implication: Software which uses the FP Data Operand Pointer and count on its value being zero after power on or

Reset without first executing an FINIT/FNINIT instruction will use an incorrect value, resulting in

incorrect behavior of the software.

Workaround: Software should follow the recommendation in Section 8.2 of the Intel Architecture Software

Developer’s Manual, Volume 3: System Programming Guide (Order Number 243192). This

recommendation states that if the FPU will be used, software-initialization code should execute an

FINIT/FNINIT instruction following a hardware reset. This will correctly clear the FP Data Operand

Pointer to zero.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

M16.

MOVD Following Zeroing Instruction Can Cause Incorrect Result

Problem: An incorrect result may be calculated after the following circumstances occur:

1. A register has been zeroed with either a SUB reg, reg instruction or an XOR reg, reg instruction,

2. A value is moved with sign extension into the same register’s lower 16 bits; or a signed integer

multiply is performed to the same register’s lower 16 bits,

3. This register is then copied to an MMX™ technology register using the MOVD instruction prior to

any other operations on the sign-extended value.

Specifically, the sign may be incorrectly extended into bits 16-31 of the MMX technology register. Only

the MMX technology register is affected by this erratum.

The erratum only occurs when the 3 following steps occur in the order shown. The erratum may occur

with up to 40 intervening instructions that do not modify the sign-extended value between steps 2 and 3.

1. XOR EAX, EAX

or SUB EAX, EAX

2. MOVSX AX, BL

or MOVSX AX, byte ptr <memory address> or MOVSX AX, BX

or MOVSX AX, word ptr <memory address> or IMUL BL (AX implicit, opcode F6 /5)

or IMUL byte ptr <memory address> (AX implicit, opcode F6 /5) or IMUL AX, BX (opcode 0F AF /r)

or IMUL AX, word ptr <memory address> (opcode 0F AF /r) or IMUL AX, BX, 16 (opcode 6B /r ib)

or IMUL AX, word ptr <memory address>, 16 (opcode 6B /r ib) or IMUL AX, 8 (opcode 6B /r ib)

or IMUL AX, BX, 1024 (opcode 69 /r iw)

or IMUL AX, word ptr <memory address>, 1024 (opcode 69 /r iw) or IMUL AX, 1024 (opcode 69 /r iw)

or CBW

3. MOVD MM0, EAX

Note that the values for immediate byte/words are merely representative (i.e., 8, 16, 1024) and that any

value in the range for the size may be affected. Also, note that this erratum may occur with “EAX”

replaced with any 32-bit general purpose register, and “AX” with the corresponding 16-bit version of

that replacement. “BL” or “BX” can be replaced with any 8-bit or 16-bit general-purpose register. The

CBW and IMUL (opcode F6 /5) instructions are specific to the EAX register only.