Specification Update

32 Mobile Intel® Celeron® Processor Specification Update

In the example, EAX is forced to contain 0 by the XOR or SUB instructions. Since the four types of the

MOVSX or IMUL instructions and the CBW instruction modify only bits 15:8 of EAX by sign

extending the lower 8 bits of EAX, bits 31:16 of EAX should always contain 0. This implies that when

MOVD copies EAX to MM0, bits 31:16 of MM0 should also be 0. Under certain scenarios, bits 31:16 of

MM0 are not 0, but are replicas of bit 15 (the 16th bit) of AX. This is noticeable when the value in AX

after the MOVSX, IMUL or CBW instruction is negative, i.e., bit 15 of AX is a 1.

When AX is positive (bit 15 of AX is a 0), MOVD will always produce the correct answer. If AX is

negative (bit 15 of AX is a 1), MOVD may produce the right answer or the wrong answer depending on

the point in time when the MOVD instruction is executed in relation to the MOVSX, IMUL or CBW

instruction.

Implication: The effect of incorrect execution will vary from unnoticeable, due to the code sequence discarding the

incorrect bits, to an application failure. If the MMX technology-enabled application in which MOVD is

used to manipulate pixels, it is possible for one or more pixels to exhibit the wrong color or position

momentarily. It is also possible for a computational application that uses the MOVD instruction in the

manner described above to produce incorrect data. Note that this data may cause an unexpected page

fault or general protection fault.

Workaround: There are two possible workarounds for this erratum:

1. Rather than using the MOVSX-MOVD, IMUL-MOVD or CBW-MOVD pairing to handle one

variable at a time, use the sign extension capabilities (PSRAW, etc.) within MMX technology for

operating on multiple variables. This would result in higher performance as well.

2. Insert another operation that modifies or copies the sign-extended value between the

MOVSX/IMUL/CBW instruction and the MOVD instruction as in the example below:

XOR EAX, EAX (or SUB EAX, EAX)

MOVSX AX, BL (or other MOVSX, other IMUL or CBW instruction)

*MOV EAX, EAX

MOVD MM0, EAX

MOV EAX, EAX is used here as it is fairly generic. Again, EAX can be any 32-bit register.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

M17.

Premature Execution of a Load Operation Prior to Exception Handler Invocation

Problem: This erratum can occur with any of the following situations:

1. If an instruction that performs a memory load causes a code segment limit violation,

2. If a waiting floating-point instruction or MMX instruction that performs a memory load has a

floating-point exception pending, or

3. If an MMX instruction that performs a memory load and has either CR0.EM =1 (Emulation bit set),

or a floating-point Top-of-Stack (FP TOS) not equal to 0, or a DNA exception pending.

If any of the above circumstances occur it is possible that the load portion of the instruction will have

executed before the exception handler is entered.

Implication: In normal code execution where the target of the load operation is to write back memory there is no

impact from the load being prematurely executed, nor from the restart and subsequent re-execution of

that instruction by the exception handler. If the target of the load is to uncached memory that has a

system side-effect, restarting the instruction may cause unexpected system behavior due to the repetition

of the side-effect.