Specification Update

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Mobile Intel® Celeron® Processor Specification Update 33
Workaround: Code which performs loads from memory that has side-effects can effectively workaround this behavior
by using simple integer-based load instructions when accessing side-effect memory and by ensuring that
all code is written such that a code segment limit violation cannot occur as a part of reading from side-
effect memory.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M18.
Read Portion of RMW Instruction May Execute Twice
Problem: When the mobile processor executes a read-modify-write (RMW) arithmetic instruction, with memory
as the destination, it is possible for a page fault to occur during the execution of the store on the memory
operand after the read operation has completed but before the write operation completes.
If the memory targeted for the instruction is UC (uncached), memory will observe the occurrence of the
initial load before the page fault handler and again if the instruction is restarted.
Implication: This erratum has no effect if the memory targeted for the RMW instruction has no side effects. If,
however, the load targets a memory region that has side effects, multiple occurrences of the initial load
may lead to unpredictable system behavior.
Workaround: Hardware and software developers who write device drivers for custom hardware that may have a side-
effect style of design should use simple loads and simple stores to transfer data to and from the device.
Then, the memory location will simply be read twice with no additional implications.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M19.
MC2_STATUS MSR Has Model-Specific Error Code and Machine Check
Architecture Error Code Reversed
Problem: The Intel Architecture Software Developer’s Manual, Volume 3: System Programming Guide,
documents that for the MCi_STATUS MSR, bits 15:0 contain the MCA (machine-check architecture)
error code field, and bits 31:16 contain the model-specific error code field. However, for the
MC2_STATUS MSR, these bits have been reversed. For the MC2_STATUS MSR, bits 15:0 contain the
model-specific error code field and bits 31:16 contain the MCA error code field.
Implication: A machine check error may be decoded incorrectly if this erratum on the MC2_STATUS MSR is not
taken into account.
Workaround: When decoding the MC2_STATUS MSR, reverse the two error fields.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M20.
MOV With Debug Register Causes Debug Exception
Problem: When in V86 mode, if a MOV instruction is executed on debug registers, a general-protection exception
(#GP) should be generated, as documented in the Intel Architecture Software Developer's Manual,
Volume 3: System Programming Guide, Section 14.2. However, in the case when the general detect
enable flag (GD) bit is set, the observed behavior is that a debug exception (#DB) is generated instead.
Implication: With debug-register protection enabled (i.e., the GD bit set), when attempting to execute a MOV on
debug registers in V86 mode, a debug exception will be generated instead of the expected general-
protection fault.
Workaround: In general, operating systems do not set the GD bit when they are in V86 mode. The GD bit is generally
set and used by debuggers. The debug exception handler should check that the exception did not occur in