Specification Update

R
34 Mobile Intel® Celeron® Processor Specification Update
V86 mode before continuing. If the exception did occur in V86 mode, the exception may be directed to
the general-protection exception handler.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M21.
Upper Four PAT Entries Not Usable With Mode B or Mode C Paging
Problem: The Page Attribute Table (PAT) contains eight entries, which must all be initialized and considered
when setting up memory types for the mobile processor. However, in Mode B or Mode C paging, the
upper four entries do not function correctly for 4-Kbyte pages. Specifically, bit seven of page table
entries that translate addresses to 4-Kbyte pages should be used as the upper bit of a three-bit index to
determine the PAT entry that specifies the memory type for the page. When Mode B (CR4.PSE = 1)
and/or Mode C (CR4.PAE) are enabled, the processor forces this bit to zero when determining the
memory type regardless of the value in the page table entry. The upper four entries of the PAT function
correctly for 2-Mbyte and 4-Mbyte large pages (specified by bit 12 of the page directory entry for those
translations).
Implication: Only the lower four PAT entries are useful for 4-KB translations when Mode B or C paging is used. In
Mode A paging (4-Kbyte pages only), all eight entries may be used. All eight entries may be used for
large pages in Mode B or C paging.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M22.
Data Breakpoint Exception in a Displacement Relative Near Call May Corrupt EIP
Problem: If a misaligned data breakpoint is programmed to the same cache line as the memory location where the
stack push of a near call is performed and any data breakpoints are enabled, the processor will update the
stack and ESP appropriately, but may skip the code at the destination of the call. Hence, program
execution will continue with the next instruction immediately following the call, instead of the target of
the call.
Implication: The failure mechanism for this erratum is that the call would not be taken; therefore, instructions in the
called subroutine would not be executed. As a result, any code relying on the execution of the subroutine
will behave unpredictably.
Workaround: Whether enabled or not, do not program a misaligned data breakpoint to the same cache line on the stack
where the push for the near call is performed.
Status: For the stepping affected see the Summary of Changes at the beginning of this section.
M23.
RDMSR or WRMSR to Invalid MSR Address May Not Cause GP Fault
Problem: The RDMSR and WRMSR instructions allow reading or writing of MSRs (Model Specific Registers)
based on the index number placed in ECX. The processor should reject access to any reserved or
unimplemented MSRs by generating #GP(0). However, there are some invalid MSR addresses for which
the processor will not generate #GP(0).
Implication: For RDMSR, undefined values will be read into EDX:EAX. For WRMSR, undefined processor behavior
may result.
Workaround: Do not use invalid MSR addresses with RDMSR or WRMSR.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.