Specification Update

R
36 Mobile Intel® Celeron® Processor Specification Update
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M27.
Misaligned Locked Access to APIC Space Results in Hang
Problem: When the processor’s APIC space is accessed with a misaligned locked access a machine check
exception is expected. However, the processor’s machine check architecture is unable to handle the
misaligned locked access.
If this erratum occurs the processor will hang. Typical usage models for the APIC address space do not
use locked accesses. This erratum will not affect systems using such a model.
Workaround: Ensure that all accesses to APIC space are aligned.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M28.
Processor May Assert DRDY# on a Write with No Data
Problem: When a MASKMOVQ instruction is misaligned across a chunk boundary in a way that one chunk has a
mask of all 0’s, the processor will initiate two partial write transactions with one having all byte enables
deasserted. Under these conditions, the expected behavior of the processor would be to perform both
write transactions, but to deassert DRDY# during the transaction which has no byte enables asserted. As
a result of this erratum, DRDY# is asserted even though no data is being transferred.
Implication: The implications of this erratum depend on the bus agent’s ability to handle this erroneous DRDY#
assertion. If a bus agent cannot handle a DRDY# assertion in this situation, or attempts to use the invalid
data on the bus during this transaction, unpredictable system behavior could result.
Workaround:
A system which can accept a DRDY# assertion during a write with no data will not be affected by this
erratum. In addition, this erratum will not occur if the MASKMOVQ is aligned.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M29.
GP# Fault on WRMSR to ROB_CR_BKUPTMPDR6
Problem: Writing a ‘1’ to unimplemented bit(s) in the ROB_CR_BKUPTMPDR6 MSR (offset 1E0h) will result in
a general protection fault (GP#).
Implication: The normal process used to write an MSR is to read the MSR using RDMSR, modify the bit(s) of
interest, and then to write the MSR using WRMSR. Because of this erratum, this process may result in a
GP# fault when used to modify the ROB_CR_BKUPTMPDR6 MSR.
Workaround: When writing to ROB_CR_BKUPTMPDR6 all unimplemented bits must be ‘0.’ Implemented bits may
be set as ‘0’ or ‘1’ as desired.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M30.
Machine Check Exception May Occur Due to Improper Line Eviction in the IFU
Problem: The mobile processor is designed to signal an unrecoverable Machine Check Exception (MCE) as a
consistency checking mechanism. Under a complex set of circumstances involving multiple speculative
branches and memory accesses there exists a one cycle long window in which the processor may signal a
MCE in the Instruction Fetch Unit (IFU) because instructions previously decoded have been evicted
from the IFU. The one cycle long window is opened when an opportunistic fetch receives a partial hit on
a previously executed but not as yet completed store resident in the store buffer. The resulting partial hit