Specification Update

R
Mobile Intel® Celeron® Processor Specification Update 37
erroneously causes the eviction of a line from the IFU at a time when the processor is expecting the line
to still be present. If the MCE for this particular IFU event is disabled, execution will continue
normally.
Implication: While this erratum may occur on a system with any number of mobile processors, the probability of
occurrence increases with the number of processors. If this erratum does occur, a machine check
exception will result. Note systems that implement an operating system that does not enable the Machine
Check Architecture will be completely unaffected by this erratum (e.g., Windows95* and Windows98*).
Workaround:
It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M31.
Performance Counter L2 Prefetch Count Includes Streaming SIMD Extensions
L1 Prefetch
Problem: The processors allow the measurement of the frequency and duration of numerous different internal and
bus related events (see the Intel Architecture Software Developer's Manual, Volume 3, for more details).
The Streaming SIMD Extension (SSE) architecture provides a mechanism to pre-load data into the L1
cache, bypassing the L2 cache. The number of these L1 pre-loads measured by the performance
monitoring logic will incorrectly be included in the count of "L2_LINES_IN" (24H) events.
Implication: If application software is run which utilizes the SSE L1 prefetch feature, the count of "L2_LINES_IN"
(24H) will read a value that is greater than the correct value.
Workaround: The correct value of this counter may be calculated by taking the value read for L2_LINES_IN (24H)
and subtracting from it the value read for "EMON_KNI_PREF_MISS" (4BH, Unit Mask 00H).
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M32.
Processor Will Erroneously Report a BIST Failure
Problem: If the processor performs BIST at power-up, the EAX register is normally cleared (0H) if the processor
passes BIST. The processor will erroneously report a non-zero value (signaling a BIST failure) even if
BIST passes.
Implication: The processor will incorrectly signal an error after BIST is performed.
Workaround: The system BIOS should ignore the BIST results in the EAX register.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M33.
Internal Snooping Mechanism Causes Livelock Condition
Problem: Internal timings may align where the L2 cache snooping mechanism and the Instruction Fetch Unit
snooping mechanism reject each other’s requests to the Data Cache Unit. Both units will continue to
retry but reject requests on every other clock, leading to a livelock condition.
Implication: The system will hang. If an external agent is snooping the processor’s caches, the hang will appear as an
infinite snoop stall.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.