Specification Update

R
38 Mobile Intel® Celeron® Processor Specification Update
M34.
Cache Coherency May Be Lost If Snoop Occurs During Cache Line Invalidation
Problem: There exists a two cycle window during a cache line invalidation (due to a WBINVD instruction or
FLUSH# pin assertion) during which a processor performing a snoop of that line will not see the line in
the cache. In addition, when this erratum occurs, the processor invalidating the line will not write back
the data in that line.
Implication:
If this erratum occurs, cache coherency and data will be lost.
Workaround:
None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M35.
Extra DRDY# Assertion When Eviction Back-to-Back Write Combining Lines
Problem: The processor has the ability to evict back-to-back lines in its write combining buffers. If the processor
writes back data from L1 to L2 during a back-to-back write combining line eviction, the processor may
assert an extra DRDY# on the system bus.
Implication: Data corruption (loss of data) may occur.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M36.
Limitation on Cache Line ECC Detection and Correction
Problem: ECC can detect and correct up to four single-bit ECC errors per cache line. However, the processor will
only detect and correct one single-bit ECC error per cache line. While all ECC errors will be detected,
multiple single bit errors will be incorrectly reported as uncorrectable double bit errors, rather than
correctable single bit errors.
Implication: The processor may report fewer single bit ECC errors and more double bit ECC errors than previous
processors.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M37.
L2_LD and L2_M_LINES_OUTM Performance-Monitoring Counter Does Not
Work
Problem: The L2_LD (29h) Performance-Monitoring counter, used for counting the number of L2 cache data
loads, does not work properly.
Implication: This counter will report incorrect data.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M38.
Snoop Request May Cause DBSY# Hang
Problem: A small window of time exists in which a snoop request originating from a bus agent to a processor with
one or more outstanding memory transactions may cause the processor to assert DBSY# without issuing