Specification Update

R
40 Mobile Intel® Celeron® Processor Specification Update
M41.
L2_DBUS_BUSY Performance Monitoring Counter Will Not Count Writes
Problem: The L2_DBUS_BUSY (22H) performance monitoring counter is intended to count the number of cycles
during which the L2 data bus is in use. For some steppings of the processor, the L2_DBUS_BUSY
counter will not be incremented during write cycles and therefore will only reflect the number of L2 data
bus cycles resulting from cache reads.
Implication: The L2_DBUS_BUSY event counts only L2 read cycles.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M42.
Lower Bits of SMRAM SMBASE Register Cannot Be Written With an ITP
Problem: The System Management Base (SMBASE) register (7EF8H) stores the starting address of the System
Management RAM (SMRAM). This register is used by the processor when it is in System Management
Mode (SMM), and its contents serve as the memory base for code execution and data storage. The 32-bit
SMBASE register can normally be programmed to any value. When programmed with an In-Target
Probe (ITP), however, any attempt to set the lower 11 bits of SMBASE to anything other than zeros via
the WRMSR instruction will cause the attempted write to fail.
Implication: When set via ITP, any attempt to relocate SMRAM space must be made with 2 KB alignment.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M43.
Task Switch May Cause Wrong PTE and PDE Access Bit to be Set
Problem: If an operating system executes a task switch via a Task State Segment (TSS), and the TSS is wholly or
partially located within a clean page (A and D bits clear) and the GDT entry for the new TSS is either
misaligned across a cache line boundary or is in a clean page, the accessed and dirty bits for an incorrect
page table/directory entry may be set.
Implication: An operating system which uses hardware task switching (or hardware task management) may
encounter this erratum. The effect of the erratum depends on the alignment of the TSS and ranges from
no anomalous behavior to unexpected errors.
Workaround: The operating system could align all TSSs to be within page boundaries and set the A and D bits for
those pages to avoid this erratum. The operating system may alternately use software task management.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M44.
Unsynchronized Cross-Modifying Code Operations May Cause Unexpected
Instruction Execution Results
Problem: The act of one processor, or system bus master, writing data into a currently executing code segment of a
second processor with the intent of having the second processor execute that data as code is called cross-
modifying code (XMC). XMC that does not force the second processor to execute a synchronizing
instruction prior to execution of the new code is called unsynchronized XMC.