Specification Update

R
Mobile Intel® Celeron® Processor Specification Update 41
Software using unsynchronized XMC to modify the instruction byte stream of a processor may see
unexpected instruction execution from the processor that is executing the modified code.
Implication: In this case, the phrase "unexpected execution behavior" encompasses the generation of most of the
exceptions listed in the Intel Architecture Software Developer's Manual Volume 3: System Programming
Guide including a General Protection Fault (GPF). In the event of a GPF the application executing the
unsynchronized XMC operation would be terminated by the operating system.
Workaround: In order to avoid this erratum, programmers should use the XMC synchronization algorithm as detailed
in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, Section
7.1.3.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M45.
Deadlock May Occur Due To Illegal-Instruction/Page-Miss Combination
Problem: Intel's 32-bit Instruction Set Architecture (ISA) utilizes most of the available op-code space, however
some byte combinations remain undefined and are considered illegal instructions. Intel processors detect
the attempted execution of illegal instructions and signal an exception. This exception is handled by
operating system and/or application software.
Under a complex set of internal and external conditions involving illegal instructions, a deadlock may
occur within the processor. The necessary conditions for the deadlock involve:
1. Execution of the illegal instruction.
2. Two page table walks occur within a narrow timing window coincident with the illegal instruction.
Implication: The illegal instructions involved in this erratum are unusual and invalid byte combinations that are not
useful to application software or operating systems. These combinations are not normally generated in
the course of software programming, nor are such sequences known by Intel to be generated in
commercially available software and tools. Development tools (compilers, assemblers) do not generate
this type of code sequence, and will normally flag such a sequence as an error. If this erratum occurs,
the processor deadlock condition will occur and result in a system hang. Code execution cannot
continue without a system RESET.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M46.
MASKMOVQ Instruction Interaction with String Operation May Cause Deadlock
Problem: Under the following scenario, combined with a specific alignment of internal events, the processor may
enter a deadlock condition:
1. A store operation completes, leaving a write-combining (WC) buffer partially filled.
2. The target of a subsequent MASKMOVQ instruction is split across a cache line.
3. The data in (2) above results in a hit to the data in the WC buffer in (1).
Implication: If this erratum occurs, the processor deadlock condition will occur and result in a system hang. Code
execution cannot continue without a system RESET.
Workaround: It is possible for BIOS code to contain a workaround for this erratum.