Specification Update

42 Mobile Intel® Celeron® Processor Specification Update

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

M47.

Noise Sensitivity Issue on Processor SMI# Pin

Problem: Post silicon characterization has demonstrated a greater than expected sensitivity to noise on the

processor's SMI# input, which may result in spurious SMI# interrupts.

Implication: BIOS/SMM code that is capable of handling spurious SMI events will report a spurious SMI#, but

should not be negatively impacted by this erratum. Systems whose BIOS code cannot handle spurious

SMI events may fail, resulting in a system hang or other anomalous behavior.

Spurious SMI# interrupts should be controlled on the system board regardless of BIOS

implementation.

Workaround: Possible workarounds that may reduce or eliminate the occurrence of the spurious SMI include:

Use a lower effective pull-up resistance on the SMI# pin. This resistor must meet the specifications of

the component driving the SMI# signal.

1. Externally condition the SMI# signal prior to providing it to the processor's SMI# pin.

2. These workarounds should be evaluated on a design-by-design basis.

Status: For the steppings affected see the Summary of Changes at the beginning of this section.

M48.

MOVD, CVTSI2SS, or PINSRW Following Zeroing Instruction Can Cause

Incorrect Result

Problem: An incorrect result may be calculated after the following circumstances occur:

1. A register has been zeroed with either a SUB reg, reg instruction or an XOR reg, reg instruction,

2. A value is moved with sign extension into the same register’s lower 16 bits; or a signed integer

multiply is performed to the same register’s lower 16 bits,

3. The register is then copied to an MMX™ technology register using the MOVD, or converted to

single precision floating point and moved to an MMX technology register using the CVTSI2SS

instruction prior to any other operations on the sign-extended value.

Specifically, the sign may be incorrectly extended into bits 16-31 of the MMX technology register. This

erratum only affects the MMX technology register.

This erratum only occurs when the following three steps occur in the order shown below. This erratum

may occur with up to 40 intervening instructions that do not modify the sign-extended value between

steps 2 and 3.