Specification Update

R
44 Mobile Intel® Celeron® Processor Specification Update
Status: For the steppings affected see he Summary of Changes at the beginning of this section.
M49.
FLUSH# Assertion Following STPCLK# May Prevent CPU Clocks From Stopping
Problem: If FLUSH# is asserted after STPCLK# is asserted, the cache flush operation will not occur until after
STPCLK# is de-asserted. Furthermore, the pending flush will prevent the processor from entering the
Sleep state, since the flush operation must complete prior to the processor entering the Sleep state.
Implication: Following SLP# assertion, processor power dissipation may be higher than expected. Furthermore, if the
source to the processor’s input bus clock (BCLK) is removed, normally resulting in a transition to the
Deep Sleep state, the processor may shutdown improperly. The ensuing attempt to wake up the
processor will result in unpredictable behavior and may cause the system to hang.
Workaround: For systems that use the FLUSH# input signal and Deep Sleep state of the processor, ensure that
FLUSH# is not asserted while STPCLK# is asserted.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M50.
Intermittent Failure to Assert ADS# during Processor Power-On
Problem: Under a system specific set of initial parametric conditions, a very small number of Intel
®
Mobile
Celeron processors (CPUID 068xh) can be susceptible to entering an internal test mode during processor
power-on. The symptom of this test mode is a failure to assert ADS# during a processor power-on.
Implication: On susceptible platforms, when power is applied to the processor, there is a possibility that the processor
will occasionally enter the test mode rather than initiate a system boot sequence.
Workaround: A subsequent processor Power-Off then Power-On cycle should remove the processor from this test
mode, allowing normal processor operation to resume.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M51.
Floating-Point Exception Signal Can Be Deferred
Problem: A one clock window exists where a pending x87 FP exception that should be signaled on the execution
of a CVTPS2PI, CVTPI2PS, or CVTTPS2PI instruction can be deferred to the next waiting floating-
point instruction or instruction that would change MMX™ register state.
Implication: If this erratum occurs the floating-point exception will not be handled as expected.
Workaround: Applications that follow Intel programming guidelines (empty all x87 registers before executing MMX
technology instructions) will not be affected by this erratum.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M52.
Floating-Point Exception Condition May Be Deferred
Problem: A floating-point instruction that causes a pending floating-point exception (ES=1) is normally signaled
by the processor on the next waiting FP/MMX™ technology instruction. In the following set of
circumstances, the exception may be delayed or the FSW register may contain a wrong value:
1. The excepting floating-point instruction is followed by an instruction that accesses memory across a
page (4-Kbyte) boundary or its access results in the update of a page table dirty/access bit.