Specification Update

R
Mobile Intel® Celeron® Processor Specification Update 49
M64.
Machine Check Exception may Occur When Interleaving Code Between Different
Memory Types
Problem: A small window of opportunity exists where code fetches interleaved between different memory types
may cause a machine check exception. A complex set of micro-architectural boundary conditions is
required to expose this window.
Implication: Interleaved instruction fetches between different memory types may result in a machine check exception.
The system may hang if machine check exceptions are disabled. Intel has not observed the occurrence
of this erratum while running commercially available applications or operating systems.
Workaround: Software can avoid this erratum by placing a serializing instruction between code fetches, which span
different memory types.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M2AP. Write to Mask LVT (Programmed as EXTINT) Will Not Deassert Outstanding
Interrupt
Problem: If the APIC subsystem is configured in Virtual Wire Mode implemented through the local APIC (i.e., the
8259 INTR signal is connected to LINT0 and LVT1’s interrupt delivery mode field is programmed as
EXTINT), a write to LVT1 intended to mask interrupts will not deassert the internal interrupt source if
the external LINT0 signal is already asserted. The interrupt will be erroneously posted to the mobile
Pentium III processor despite the attempt to mask it via the LVT.
Implication: Because of the masking attempt, interrupts may be generated when the system software expects no
interrupts to be posted.
Workaround: Software can issue a write to the 8259A interrupt mask register to deassert the LINT0 interrupt level,
followed by a read to the controller to ensure that the LINT0 signal has been deasserted. Once this is
ensured, software may then issue the write to mask LVT entry 1.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M65.
Wrong ESP Register Values During a Fault in VM86 Mode
Problem: At the beginning of the IRET instruction execution in VM86 mode, the lower 16 bits of the ESP register
are saved as the old stack value. When a fault occurs, these 16 bits are moved into the 32-bit ESP,
effectively clearing the upper 16 bits of the ESP.
Implication: This erratum has not been observed to cause any problems with commercially available software.
Workaround: None identified
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M66.
APIC ICR Write May Cause Interrupt Not to be Sent When ICR Delivery Bit
Pending
Problem: If the APIC ICR (Interrupt Control Register) is written with a new interrupt command while the Delivery
Status bit from a previous interrupt command is set to '1’ (Send Pending), the interrupt message may not
be sent out by the processor.
Implication: This erratum will cause an interrupt message not to be sent, potentially resulting in system hang.