Specification Update

R
50 Mobile Intel® Celeron® Processor Specification Update
Workaround: Software should always poll
the Delivery Status bit in the APIC ICR and ensure that it is '0’ (Idle) before
writing a new value to the ICR.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.
M67.
Processor Incorrectly Samples NMI Interrupt after RESET# Deassertion When
Processor APIC is Hardware-Disabled
Problem: When the processor APIC is hardware-disabled the processor may incorrectly interpret the NMI signal
as an NMI interrupt, instead of a frequency strap value, starting six bus clocks after RESET# is de-
asserted. This will result in a processor hang due to the NMI Handler not being installed at this time.
Implication: The system may fail to boot due to this issue.
Workaround: The processor APIC must be hardware-enabled by pulling PICD[1:0] high with separate pull up resistors
and supplying PICCLK to the processor.
Status: For the steppings affected, see the Summary of Changes at the beginning of this section.
M68.
The Instruction Fetch Unit (IFU) May Fetch Instructions Based Upon Stale CR3
Data After a Write to CR3 Register
Problem: Under a complex set of conditions, there exists a one clock window following a write to the CR3 register
where-in it is possible for the iTLB fill buffer to obtain a stale page translation based on the stale CR3
data. This stale translation will persist until the next write to the CR3 register, the next page fault or
execution of a certain class of instructions including CPUID or IRETD with privilege level change.
Implication: The wrong page translation could be used leading to erroneous software behavior.
Workaround: Operating systems that are potentially affected can add a second write to the CR3 register.
Status: For the steppings affected, see the Summary of Changes at the beginning of this section.
M69.
Processor Might not Exit Sleep State Properly Upon De-assertion of CPUSLP#
Signal
Problem: If the processor enters a sleep state upon assertion of CPUSLP# signal, and if the core to system bus
multiplier is an odd bus fraction, then the processor may not resume from the CPU sleep state upon the
de-assertion of CPUSLP# signal.
Implication: This erratum may result in a system hang during a resume from CPU sleep state.
Mobile platforms using
Quick Start recommendations are not affected.
Workaround: It is possible to workaround this in BIOS by not asserting CPUSLP# for power management purposes.
For mobile platforms, the workaround is to use the Quick Start recommendation.
Status: For the steppings affected, see the Summary of Changes at the beginning of this section.
M70.
During Boundary Scan, BCLK Not Sampled High When DPSLP# is Asserted Low
Problem: During boundary scan, BCLK not sampled high when DPSLP# is asserted low.
Implication: Boundary scan results may be incorrect when DPSLP# is asserted low.