Specification Update

R
54 Mobile Intel® Celeron® Processor Specification Update
M80. Page with PAT (Page Attribute Table) Set to USWC (Uncacheable Speculative
Write Combine) While Associated MTRR (Memory Type Range Register) is UC
(Uncacheable) May Consolidate to UC
Problem: For a page whose PAT memory type is USWC while the relevant MTRR memory type is UC, the
consolidated memory type may be treated as UC (rather than WC as specified in IA-32 Intel®
Architecture Software Developer's Manual)..
Implication: When this erratum occurs, the memory page may be treated as UC (rather than WC). This may have a
negative performance impact.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
M81. Under Certain Conditions LTR (Load Task Register) Instruction May Result in
System Hang
Problem: An LTR instruction may result in a system hang if all the following conditions are met:
1. Invalid data selector of the TR (Task Register) resulting with either #GP (General Protection Fault)
or #NP (Segment Not Present Fault).
2. GDT (Global Descriptor Table) is not 8-bytes aligned.
3. Data BP (breakpoint) is set on cache line containing the descriptor data..
Implication: This erratum may result in system hang if all conditions have been met. This erratum has not been
observed in commercial operating systems or software. For performance reasons, GDT is typically
aligned to 8-bytes.
Workaround: Software should align GDT to 8-bytes
Status: For the steppings affected, see the Summary Tables of Changes.
M82. Loading from Memory Type USWC (Uncacheable Speculative Write Combine)
May Get Its Data Internally Forwarded from a Previous Pending Store
Problem: A load from memory type USWC may get its data internally forwarded from a pending store. As a
result, the expected load may never be issued to the external bus.
Implication: When this erratum occurs, a USWC Load request may be satisfied without being observed on the
external bus. There are no known usage models where this behavior results in any negative side-effects.
Workaround: Do not use memory type USWC for memory that has read side-effects.
Status: For the steppings affected, see the Summary Tables of Changes.
M83. FPU Operand Pointer may not be cleared following FINIT/FNINIT
Problem: Initializing the floating point state with either FINIT or FNINT, may not clear the x87 FPU Operand
(Data) Pointer Offset and the x87 FPU Operand (Data) Pointer Selector (both fields form the
FPUDataPointer). Saving the floating point environment with FSTENV, FNSTENV, or floating point
state with FSAVE, FNSAVE or FXSAVE before an intervening FP instruction may save uninitialized
values for the FPUDataPointer.