Manualshelf

Specification Update

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 1.00 GHz, 256K Cache, 100 MHz FSB
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Summary Tables of Changes
14 Specification Update
Stepping Stepping Stepping
Number
E-1 M-0 G-0
Plans
ERRATA
AH19 X X X No Fix Code Segment Limit Violation May Occur On 4-GB Limit Check
AH20 Fixed FP Inexact-Result Exception Flag May Not Be Set
AH21 Fixed Global Pages in the Data Translation Look-Aside Buffer (DTLB) May
Not Be Flushed by RSM instruction before Restoring the
Architectural State from SMRAM
AH22 Fixed Sequential Code Fetch to Non-canonical Address May Have
Nondeterministic Results
AH23 Fixed VMCALL to Activate Dual-monitor Treatment of SMIs and SMM
Ignores Reserved Bit Settings in VM-exit Control Field
AH24 X X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types May Use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
AH25 X X X No Fix Some Bus Performance Monitoring Events May Not Count Local
Events under Certain Conditions
AH26 X X X No Fix Premature Execution of a Load Operation Prior to Exception Handler
Invocation
AH27 X X X No Fix General Protection (#GP) Fault May Not Be Signaled on Data
Segment Limit Violation above 4-G Limit
AH28 X X X No Fix EIP May Be Incorrect after Shutdown in IA-32e Mode
AH29 X X X No Fix #GP Fault Is Not Generated on Writing IA32_MISC_ENABLE [34]
When Execute Disable Is Not supported
AH30 Removed Erratum
AH31 Fixed Performance Monitoring Events for Retired Loads (CBH) and
Instructions Retired (C0H) May Not Be Accurate
AH32 X X X No Fix Upper 32 bits of ‘From’ Address Reported through BTMs or BTSs
May Be Incorrect
AH33 Fixed Unsynchronized Cross-Modifying Code Operations Can Cause
unexpected Instruction Execution Results
AH34 X X X No Fix MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum
Frequency Clock Count (IA32_MPERF) May Contain Incorrect Data
after a Machine Check Exception (MCE)
AH35 X X X No Fix Incorrect Address Computed for Last Byte of FXSAVE/FXRSTOR
Image Leads to Partial Memory Update
AH36 X X X No Fix Split Locked Stores May Not Trigger the Monitoring Hardware
AH37 Fixed REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode
When RCX >= 0X100000000
AH38 Fixed FXSAVE/FXRSTOR Instructions which Store to the End of the
Segment and Cause a Wrap to a Misaligned Base Address
(Alignment <= 0x10h) May Cause FPU Instruction or Operand
Pointer Corruption