Manualshelf

Specification Update

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 1.00 GHz, 256K Cache, 100 MHz FSB
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Summary Tables of Changes
Specification Update 15
Stepping Stepping Stepping
Number
E-1 M-0 G-0
Plans
ERRATA
AH39 Fixed Cache Data Access Request from One Core Hitting a Modified Line
in the L1 Data Cache of the Other Core May Cause Unpredictable
System Behavior
AH40 Fixed PREFETCHh Instruction Execution under Some Conditions May Lead
to Processor Livelock
AH41 Fixed PREFETCHh Instructions May Not Be Executed when Alignment
Check (AC) Is Enabled
AH42 Fixed Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE
Memory Image May Be Unexpectedly All 1’s after FXSAVE
AH43 Fixed Concurrent Multi-processor Writes to Non-dirty Page May Result in
Unpredictable Behavior
AH44 Fixed Performance Monitor IDLE_DURING_DIV (18h) Count May Not Be
Accurate
AH45 X X X No Fix Values for LBR/BTS/BTM Will Be Incorrect after an Exit from SMM
AH46 X X X No Fix Shutdown Condition May Disable Non-Bootstrap Processors
AH47 Fixed SYSCALL Immediately after Changing EFLAGS.TF May Not Behave
According to the New EFLAGS.TF
AH48 X X X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced
before Higher Priority Interrupts/Exceptions and May Push the
Wrong Address Onto the Stack
AH49 X X X No Fix VM Bit Is Cleared on Second Fault Handled by Task Switch from
Virtual-8086 (VM86)
AH50 Fixed IA32_FMASK Is Reset during an INIT
AH51 X X X No Fix An Enabled Debug Breakpoint or Single Step Trap May Be Taken
after MOV SS/POP SS Instruction if it is Followed by an Instruction
That Signals a Floating Point Exception
AH52 X X X No Fix Last Branch Records (LBR) Updates May Be Incorrect after a Task
Switch
AH53 X X X No Fix IO_SMI Indication in SMRAM State Save Area May Be Set
Incorrectly
AH54 X X X No Fix INIT Does Not Clear Global Entries in the TLB
AH55 Fixed Using Memory Type Aliasing with Memory Types WB/WT May Lead
to Unpredictable Behavior
AH56 Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present
(P) Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
AH57 Fixed BTS Message May Be Lost When the STPCLK# Signal Is Active
AH58 X X X No Fix MOV To/From Debug Registers Causes Debug Exception
AH59 X X X No Fix EFLAGS Discrepancy on a Page Fault after a Multiprocessor TLB
Shootdown