Manualshelf

Specification Update

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 1.00 GHz, 256K Cache, 100 MHz FSB
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Summary Tables of Changes
18 Specification Update
Stepping Stepping Stepping
Number
E-1 M-0 G-0
Plans
ERRATA
AH102 Fixed Performance Monitoring Event BR_INST_RETIRED May Count
CPUID Instructions as Branches
AH103 X X X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over
Count
AH104 X X X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
AH105 Fixed False Level One Data Cache Parity Machine-Check Exceptions May
Be Signaled
AH106 X X X No Fix A Memory Access May Get a Wrong Memory Type Following a #GP
due to WRMSR to an MTRR Mask
AH107 X X X No Fix PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
AH108 X X Fixed Overlap of an Intel® VT APIC Access Page in a Guest with the DS
Save Area May Lead to Unpredictable Behavior
AH109 X X X No Fix VTPR Write Access during Event Delivery May Cause an APIC-
Access VM Exit
AH110 X X X No Fix BIST Failure after Reset
AH111 X X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
AH112 X X X No Fix Instruction Fetch May Cause a Livelock during Snoops of the L1
Data Cache
AH113 X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type May Cause
a System Hang or a Machine Check Exception
AH114 X X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to
Memory-Ordering Violations
AH115 X X X No Fix VM Exit with Exit Reason “TPR Below Threshold” Can Cause the
Blocking by MOV/POP SS and Blocking by STI Bits to Be Cleared in
the Guest Interruptability-State Field
AH116 X X X No Fix Using Memory Type Aliasing with Cacheable and WC Memory Types
May Lead to Memory Ordering Violations
AH117 X X X No Fix RSM Instruction Execution under Certain Conditions May Cause
Processor Hang or Unexpected Instruction Execution Results
AH118 X X X No Fix NMIs May Not Be Blocked by a VM-Entry Failure
AH119 X X X No Fix Benign Exception after a Double Fault May Not Cause a Triple Fault
Shutdown Problem
AH120 X X X No Fix IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check
Error Reporting Enable Correctly