Specification Update

Errata
62 Specification Update
AH110. BIST Failure after Reset
Problem: The processor may show an erroneous BIST (built-in self test) result in bit [17] of EAX
register when coming out of reset.
Implication: When this erratum occurs, an erroneous BIST failure will be reported in EAX bit [17].
This failure can be ignored since it is not accurate.
Workaround: It is possible for BIOS to workaround this erratum by masking off bit [17] of the EAX
register after coming out of reset.
Status: For the steppings affected, see the Summary Tables of Changes.
AH111. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H)
counts transitions from x87 Floating Point (FP) to MMX™ technology instructions. Due
to this erratum, if only a small number of MMX technology instructions (including
EMMS) are executed immediately after the last FP instruction, a FP to MMX technology
transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be
lower than expected. The degree of undercounting is dependent on the occurrences of
the erratum condition while the counter is active. Intel has not observed this erratum
with any commercially-available software.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AH112. Instruction Fetch May Cause a Livelock during Snoops of the L1 Data
Cache
Problem: A livelock may be observed in rare conditions when instruction fetch causes multiple
level one data cache snoops.
Implication: Due to this erratum, a livelock may occur. Intel has not observed this erratum with
any commercially-available software.
Workaround: It is possible for BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.