Specification Update

Identification Information

Specification Update 7

Identification Information

Component Identification via Programming Interface

The Intel Celeron Dual-Core processor stepping can be identified by the following

Family

Model

Model for A-1 step

0110 1111 10000

NOTES:

1. The family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the

EAX register after the CPUID instruction is executed with a 1 in the EAX register, and

the generation field of the Device ID registers accessible through boundary scan.

2. The model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the

EAX register after the CPUID instruction is executed with a 1 in the EAX register, and

the model field of the device ID registers accessible through boundary scan.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX, and EDX

registers after the CPUID instruction is executed with a 2 in the EAX register. Refer to

the Intel Processor Identification and the CPUID Instruction Application Note (AP-485)

and the latest Intel® Core™ 2 Duo Mobile Processor BIOS Writer’s Guide for further

information on the CPUID instruction.

Each stepping of the Intel Celeron Dual-Core processor can be identified by software

with its CPU signature:

Stepping CPU Signature

M-0 06FDh