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Specification Update

ManualsBrandsIntel ManualsOtherIntel Celeron Processor 1.00 GHz, 256K Cache, 100 MHz FSB
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Summary Tables of Changes
Specification Update 15
Errata
Steppings
Number
C-0 M-0 E-0
Status ERRATA
AZ1 X X X No Fix EFLAGS Discrepancy on a Page Fault After a Multiprocessor TLB
Shootdown
AZ2 X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete
under Certain Conditions
AZ3 X X X No Fix Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
AZ4 X X X No Fix Non-Temporal Data Store May be Observed in Wrong Program
Order
AZ5 X X X No Fix Page Access Bit May be Set Prior to Signaling a Code Segment
Limit Fault
AZ6 X X X No Fix Updating Code Page Directory Attributes without TLB Invalidation
May Result in Improper Handling of Code #PF
AZ7 X X X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or
STI
AZ8 X X X No Fix Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
AZ9 X X X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May
Prevent Triggering of the Monitoring Hardware
AZ10 X X X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over
Count
AZ11 X X X No Fix The Processor May Report a #TS Instead of a #GP Fault
AZ12 X X X No Fix Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
AZ13 X X X No Fix A Write to an APIC Register Sometimes May Appear to Have Not
Occurred
AZ14 X X X No Fix Last Branch Records (LBR) Updates May be Incorrect after a Task
Switch
AZ15 X X X No Fix REP MOVS/STOS Executing with Fast Strings Enabled and Crossing
Page Boundaries with Inconsistent Memory Types may use an
Incorrect Data Size or Lead to Memory-Ordering Violations.
AZ16 X X X No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs
May be Incorrect
AZ17 X X X No Fix Address Reported by Machine-Check Architecture (MCA) on Single-
bit L2 ECC Errors May be Incorrect
AZ18 X X X No Fix Code Segment Limit/Canonical Faults on RSM May be Serviced
before Higher Priority Interrupts/Exceptions
AZ19 X X X No Fix Store Ordering May be Incorrect between WC and WP Memory Type
AZ20 X X X No Fix EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after
Shutdown