Specification Update

Summary Tables of Changes
18 Specification Update
Steppings
Number
C-0 M-0 E-0
Status ERRATA
AZ63 X No Fix INIT Incorrectly Resets IA32_LSTAR MSR
AZ64 X No Fix When a CPUID instruction is executed, the returned EAX, EBX, ECX,
and/or EDX may be incorrect.
AZ65 X X X No Fix Global Instruction TLB Entries May Not be Invalidated on a VM Exit
or VM Entry
AZ66 X No Fix XRSTOR Instruction May Cause Extra Memory Reads
AZ67 X X X No Fix LBR, BTS, BTM May Report a Wrong Address when an
Exception/Interrupt Occurs in 64-bit Mode
AZ68 X No Fix When Intel® Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
AZ69 X No Fix Enabling PECI via the PECI_CTL MSR Incorrectly
Writes CPUID_FEATURE_MASK1 MSR
AZ70 X X X No Fix Corruption of CS Segment Register During RSM While Transitioning
From Real Mode to Protected Mode
AZ71 X No Fix The XSAVE Instruction May Erroneously Set Reserved Bits in the
XSTATE_BV Field
AZ72 X No Fix Store Ordering Violation When Using XSAVE
AZ73 X X X No Fix Memory Ordering Violation With Stores/Loads Crossing a Cacheline
Boundary
AZ74 X No Fix The XRSTOR Instruction May Fail to Cause a General-Protection
Exception
AZ75 X X X No Fix B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly
Set
Number SPECIFICATION CHANGES
There are no Specification Changes in this Specification Update revision
Number SPECIFICATION CLARIFICATIONS
AZ1
Clarification of Translation Lookaside Buffers (TLBS) Invalidation
AZ2
CPUID Instruction Will Return Brand String With a Missing Letter
Number DOCUMENTATION CHANGES
There are no Documentation Changes in this Specification Update revision.
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