Specification Update

Errata
50 Specification Update
AZ75. B0-B3 Bits in DR6 for Non-Enabled Breakpoints May be Incorrectly Set
Problem: Some of the B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may be
incorrectly set for non-enabled breakpoints when the following sequence happens:
1. MOV or POP instruction to SS (Stack Segment) selector;
2. Next instruction is FP (Floating Point) that gets FP assist
3. Another instruction after the FP instruction completes successfully
4. A breakpoint occurs due to either a data breakpoint on the preceding instruction or a
code
breakpoint on the next instruction.
Due to this erratum a non-enabled breakpoint triggered on step 1 or step 2 may be
reported in B0-B3 after the breakpoint occurs in step 4.
Implication: Due to this erratum, B0-B3 bits in DR6 may be incorrectly set for non-enabled
breakpoints
Workaround: Software should not execute a floating point instruction directly after a MOV SS or POP
SS instruction
Status: For the steppings affected, see the Summary Tables of Changes.
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