Datasheet

Introduction and Features Summary
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
10 Document Number: 323178-003
1.2 Interfaces
1.2.1 System Memory Support
One or two channels of DDR3 memory with a maximum of one DIMM per channel
Single- and dual-channel memory organization modes
Data burst length of eight for all memory organization modes
Memory DDR3 data transfer rates of 800 and 1066 MT/s
64-bit wide channels (72-bit wide including ECC)
DDR3 I/O Voltage of 1.5 V
Supports ECC and non-ECC, unbuffered DDR3 DIMMs
Mixing of ECC and Non-ECC DIMMS is not supported
Theoretical maximum memory bandwidth of:
12.8 GB/s in dual-channel mode assuming DDR3 800 MT/s
17.1 GB/s in dual-channel mode assuming DDR3 1066 MT/s
1-Gb, and 2-Gb DDR3 DRAM technologies for x8 and x16 devices
Using 2-Gb device technologies, the largest memory capacity possible is 8 GB,
assuming dual-channel mode with two x8, dual-rank, un-buffered, DIMM memory
configuration.
Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank
Devices)
Memory organizations:
Single-channel modes
Dual-channel modes
Dual-channel symmetric (Interleaved)
Dual-channel asymmetric
Intel
®
Flex Memory Technology
Command launch mode of 1n
Partial Writes to memory using Data Mask (DM) signals
On-Die Termination (ODT)
•Intel
®
Fast Memory Access (Intel
®
FMA):
Just-in-Time Command Scheduling
—Command Overlap
Out-of-Order Scheduling
1.2.2 PCI Express*
The processor PCI Express* port(s) are fully-compliant to the PCI Express Base
Specification, Revision 2.0 at 2.5GT/s.
The processor supports:
One 16-lane PCI Express port for graphics or I/O.
Two 8-lane PCI Express ports for graphics or I/O.
PCI Express Port 0 is mapped to PCI Device 1.
PCI Express Port 1 is mapped to PCI Device 6.