Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
106 Document Number: 323178-003
6.2.26 PM_CS6 - Power Management Control/Status
B/D/F/Type: 0/6/0/PCI
Address Offset: 84-87h
Default Value: 00000008h
Access: RO; RW-S; RW
Size: 32 bits
Table 49. PM_CS6 - Power Management Control/Status Register
Bit Access Default
Value
RST/
PWR
Description
31:16 RO 0000h Core Reserved
Not Applicable or Implemented. Hard wired to 0.
15 RO 0b Core PME Status (PMESTS)
Indicates that this device does not support PMEB generation from
D3cold.
14:13 RO 00b Core Data Scale (DSCALE)
Indicates that this device does not support the power
management data register.
12:9 RO 0h Core Data Select (DSEL)
Indicates that this device does not support the power
management data register.
8RW-S 0b CorePME Enable (PMEE)
Indicates that this device does not generate PMEB assertion from
any D-state.0:PMEB generation not possible from any D State
1 = PMEB generation enabled from any D State
The setting of this bit has no effect on hardware.See
PM_CAP[15:11]
7:4 RO 0000b Core Reserved
3RO 1bCoreNo Soft Reset (NSR)
When set to 1 this bit indicates that the device is transitioning
from D3hot to D0 because the power state commands do not
perform an internal reset. Config context is preserved. Upon
transition no additional operating sys intervention is required to
preserve configuration context beyond writing the power state
bits.
When clear the devices do not perform an internal reset upon
transitioning from D3hot to D0 via software control of the power
state bits.
Regardless of this bit, the devices that transition from a D3hot to
D0 by a system or bus segment reset will return to the device
state D0 un-initialized with only PME context preserved if PME is
supported and enabled.
2RO 0bCoreReserved