Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
110 Document Number: 323178-003
6:4 RW 000b Core Multiple Message Enable (MME)
System software programs this field to indicate the actual number
of messages allocated to this device. This number is equal to or
less than the number actually requested. The encoding is the
same as for the MMC field below.
3:1 RO 000b Core Multiple Message Capable (MMC)
System software reads this field to determine the number of
messages being requested by this device. Value:Number of
Messages Requested
000: 1
All of the following are reserved in this implementation: 001:2
010: 4
011: 8
100: 16
101: 32
110: Reserved
111: Reserved
0RW 0bCoreMSI Enable (MSIEN)
Controls the ability of this device to generate MSIs.
0 = MSI will not be generated.
1 = MSI is generated when we receive PME or HotPlug messages.
INTA will not be generated and INTA Status (PCISTS6[3]) will
not be set.
Table 53. MC - Message Control Register (Sheet 2 of 2)
Bit Access Default
Value
RST/
PWR
Description