Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 113
Processor Configuration Registers
6.2.35 DCAP - Device Capabilities
B/D/F/Type: 0/6/0/PCI
Address Offset: A4-A7h
Default Value: 00008000h
Access: RO
Size: 32 bits
Indicates PCI Express device capabilities.
3:0 RO 2h Core PCI Express Capability Version (PCIECV)
hard wired to 2h to indicate compliance to the PCI Express
Capabilities Register Expansion ECN.
Table 57. PEG_CAP - PCI Express-G Capabilities Register
Bit Access
Default
Value
RST/
PWR
Description
Table 58. DCAP - Device Capabilities Register
Bit Access
Default
Value
RST/
PWR
Description
31:16 RO 0000h Core Reserved
Not Applicable or Implemented. Hard wired to 0.
15 RO 1b Core Role-Based Error Reporting (RBER)
Indicates that this device implements the functionality defined
in the Error Reporting ECN as required by the PCI Express Base
spec.
14:6 RO 000h Core Reserved
Not Applicable or Implemented. Hard wired to 0.
5RO 0bCoreExtended Tag Field Supported (ETFS)
hard wired to indicate support for 5-bit Tags as a Requestor.
4:3 RO 00b Core Phantom Functions Supported (PFS)
Not Applicable or Implemented. Hard wired to 0.
2:0 RO 000b Core Max Payload Size (MPS)
hard wired to indicate 128B max supported payload for
Transaction Layer Packets (TLP).