Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
114 Document Number: 323178-003
6.2.36 DCTL - Device Control
B/D/F/Type: 0/6/0/PCI
Address Offset: A8-A9h
Default Value: 0000h
Access: RO; RW
Size: 16 bits
Provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
Table 59. DCTL - Device Control Register (Sheet 1 of 2)
Bit Access
Default
Value
RST/
PWR
Description
15 RO 0h Core Reserved
14:12 RO 000b Core Reserved for Max Read Request Size (MRRS)
11 RO 0b Core Reserved for Enable No Snoop (RSVD)
10 RO 0b Core Reserved
Reserved for Auxiliary (AUX) PM Enable ()
9RO 0bCoreReserved
Reserved for Phantom Functions Enable ()
8RO 0bCoreReserved
Reserved for Extended Tag Field Enable ()
7:5 RW 000b Core Max Payload Size (MPS)
000:128B max supported payload for Transaction Layer Packets
(TLP). As a receiver, the Device must handle TLPs as large as the
set value; as transmitter, the Device must not generate TLPs
exceeding the set value.
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to
support compliance testing.
4RO 0bCoreReserved for Enable Relaxed Ordering (RSVD)
3RW 0bCoreUnsupported Request Reporting Enable (URRE)
When set, allows signaling ERR_NONFATAL, ERR_FATAL, or
ERR_CORR to the Root Control register when detecting an
unmasked Unsupported Request (UR). An ERR_CORR is signaled
when an unmasked Advisory Non-Fatal UR is received. An
ERR_FATAL or ERR_NONFATAL is sent to the Root Control register
when an uncorrectable non-Advisory UR is received with the
severity bit set in the Uncorrectable Error Severity register.
2RW 0bCoreFatal Error Reporting Enable (FERE)
When set, enables signaling of ERR_FATAL to the Root Control
register due to internally detected errors or error messages
received across the link. Other bits also control the full scope of
related error reporting.