Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
116 Document Number: 323178-003
6.2.38 LCAP - Link Capabilities
B/D/F/Type: 0/6/0/PCI
Address Offset: AC-AFh
Default Value: 03214C81h
Access: RO; RW-O
Size: 32 bits
Indicates PCI Express device specific capabilities.
2RWC 0b CoreFatal Error Detected (FED)
When set this bit indicates that fatal error(s) were
detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device
Control register. When Advanced Error Handling is
enabled, errors are logged in this register regardless of
the settings of the uncorrectable error mask register.
1RWC 0b CoreNon-Fatal Error Detected (NFED)
When set this bit indicates that non-fatal error(s) were
detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device
Control register.
When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the
uncorrectable error mask register.
0RWC 0b CoreCorrectable Error Detected (CED)
When set this bit indicates that correctable error(s) were
detected. Errors are logged in this register regardless of
whether error reporting is enabled or not in the Device
Control register.
When Advanced Error Handling is enabled, errors are
logged in this register regardless of the settings of the
correctable error mask register.
Table 60. DSTS - Device Status Register
Bit Access
Default
Value
RST/
PWR
Description
Table 61. LCAP - Link Capabilities Register (Sheet 1 of 3)
Bit Access
Default
Value
RST/
PWR
Description
31:24 RO 03h Core Port Number (PN)
Indicates the PCI Express port number for the given PCI Express
link. Matches the value in Element Self Description[31:24].
23:22 RO 00b Core Reserved