Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 119
Processor Configuration Registers
6.2.39 LCTL - Link Control
B/D/F/Type: 0/6/0/PCI
Address Offset: B0-B1h
Default Value: 0000h
Access: RO; RW; RW-SC
Size: 16 bits
Allows control of PCI Express link.
Table 62. LCTL - Link Control Register (Sheet 1 of 3)
Bit Access Default
Value
RST/
PWR
Description
15:12 RO 0000b Core Reserved
11 RW 0b Core Link Autonomous Bandwidth Interrupt Enable (LABIE)
When Set, this bit enables the generation of an interrupt to
indicate that the Link Autonomous Bandwidth Status bit has been
Set.
This bit is not applicable and is reserved for Endpoint devices, PCI
Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
Devices that do not implement the Link Bandwidth Notification
capability must hardwire this bit to 0b.
10 RW 0b Core Link Bandwidth Management Interrupt Enable (LBMIE)
When Set, this bit enables the generation of an interrupt to
indicate that the Link Bandwidth Management Status bit has been
Set.
This bit is not applicable and is reserved for Endpoint devices, PCI
Express to PCI/PCI-X bridges, and Upstream Ports of Switches.
9RW 0bCoreHardware Autonomous Width Disable (HAWD)
When Set, this bit disables hardware from changing the Link
width for reasons other than attempting to correct unreliable Link
operation by reducing Link width.
Devices that do not implement the ability autonomously to
change Link width are permitted to hardwire this bit to 0b.
8RO 0bCoreEnable Clock Power Management (ECPM)
Applicable only for form factors that support a “Clock Request”
(CLKREQ#) mechanism, this enable functions as follows:
0b – Clock power management is disabled and device must hold
CLKREQ# signal low.
1b - When this bit is set to 1 the device is permitted to use
CLKREQ# signal to power manage link clock according to protocol
defined in appropriate form factor specification.
Default value of this field is 0b. Components that do not support
Clock Power Management (as indicated by a 0b value in the Clock
Power Management bit of the Link Capabilities Register) must
hardwire this bit to 0b.