Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 121
Processor Configuration Registers
6.2.40 LSTS - Link Status
B/D/F/Type: 0/6/0/PCI
Address Offset: B2-B3h
Default Value: 1000h
Access: RWC; RO
Size: 16 bits
Indicates PCI Express link status.
1:0 RW 00b Core Active State PM (ASPM)
Controls the level of active state power management supported
on the given link.
00: Disabled
01: L0s Entry Supported
10: L1 Entry Enabled
11: L0s and L1 Entry Supported
Note: “L0s Entry Enabled” indicates the Transmitter entering L0s
is supported. The Receiver must be capable of entering L0s even
when the field is disabled (00b).
ASPM L1 must be enabled by software in the Upstream
component on a Link prior to enabling ASPM L1 in the
Downstream component on that Link. When disabling ASPM L1,
software must disable ASPM L1 in the Downstream component on
a Link prior to disabling ASPM L1 in the Upstream component on
that Link. ASPM L1 must only be enabled on the Downstream
component if both components on a Link support ASPM L1.
Table 62. LCTL - Link Control Register (Sheet 3 of 3)
Bit Access Default
Value
RST/
PWR
Description
Table 63. LSTS - Link Status Register (Sheet 1 of 3)
Bit Access
Default
Value
RST/
PWR
Description
15 RWC 0b Core Link Autonomous Bandwidth Status (LABWS)
This bit is set to 1b by hardware to indicate that hardware has
autonomously changed link speed or width, without the port
transitioning through DL_Down status, for reasons other than to
attempt to correct unreliable link operation.
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was
indicated as an autonomous change.
This bit must be set when the upstream component receives eight
consecutive TS1 or TS2 ordered sets with the Autonomous
Change bit set.