Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
122 Document Number: 323178-003
14 RWC 0b Core Link Bandwidth Management Status (LBWMS)
This bit is set to 1b by hardware to indicate that either of the
following has occurred without the port transitioning through
DL_Down status: A link retraining initiated by a write of 1b to the
Retrain Link bit has completed.
Note: This bit is Set following any write of 1b to the Retrain Link
bit, including when the Link is in the process of retraining for
some other reason.
Hardware has autonomously changed link speed or width to
attempt to correct unreliable link operation, either through an
LTSSM timeout or a higher level process
This bit must be set if the Physical Layer reports a speed or width
change was initiated by the downstream component that was not
indicated as an autonomous change.
13 RO 0b Core Data Link Layer Link Active (Optional) (DLLLA)
This bit indicates the status of the Data Link Control and
Management State Machine. It returns a 1b to indicate the
DL_Active state, 0b otherwise. This bit must be implemented if
the corresponding Data Link Layer Active Capability bit is
implemented. Otherwise, this bit must be hard wired to 0b.
12 RO 1b Core Slot Clock Configuration (SCC)
0 = The device uses an independent clock irrespective of the
presence of a reference on the connector.
1 = The device uses the same physical reference clock that the
platform provides on the connector.
11 RO 0b Core Link Training (LTRN)
Indicates that the Physical Layer LTSSM is in the Configuration or
Recovery state, or that 1b was written to the Retrain Link bit but
Link training has not yet begun. Hardware clears this bit when the
LTSSM exits the Configuration/Recovery state once Link training
is complete.
10 RO 0b Core Undefined (Undefined)
The value read from this bit is undefined. In previous versions of
this specification, this bit was used to indicate a Link Training
Error. System software must ignore the value read from this bit.
System software is permitted to write any value to this bit.
9:4 RO 00h Core Negotiated Link Width (NLW)
Indicates negotiated link width. This field is valid only when the
link is in the L0, L0s, or L1 states (after link width negotiation is
successfully completed).
00h: Reserved
01h: X1
02h: X2
04h: X4
08h: X8
10h: X16
All other encodings are reserved.
Table 63. LSTS - Link Status Register (Sheet 2 of 3)
Bit Access
Default
Value
RST/
PWR
Description