Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
128 Document Number: 323178-003
5RO 0bCoreReserved for MRL Sensor State (MSS)
This register reports the status of the MRL sensor if it is
implemented.
Defined encodings are:
0b MRL Closed
1b MRL Open
4RO 0bCoreReserved for Command Completed (CC)
If Command Completed notification is supported (as indicated by
No Command Completed Support field of Slot Capabilities
Register), this bit is set when a hot-plug command has
completed and the Hot-Plug Controller is ready to accept a
subsequent command. The Command Completed status bit is
set as an indication to host software that the Hot-Plug Controller
has processed the previous command and is ready to receive the
next command; it provides no guarantee that the action
corresponding to the command is complete.
If Command Completed notification is not supported, this bit
must be hard wired to 0b.
3RWC 0b CorePresence Detect Changed (PDC)
A pulse indication that the inband presence detect state has
changed. This bit is set when the value reported in Presence
Detect State is changed.
2RO 0bCoreReserved for MRL Sensor Changed (MSC)
If an MRL sensor is implemented, this bit is set when a MRL
Sensor state change is detected. If an MRL sensor is not
implemented, this bit must not be set.
1RO 0bCoreReserved for Power Fault Detected (PFD)
If a Power Controller that supports power fault detection is
implemented, this bit is set when the Power Controller detects a
power fault at this slot. Note that, depending on hardware
capability, it is possible that a power fault can be detected at any
time, independent of the Power Controller Control setting or the
occupancy of the slot. If power fault detection is not supported,
this bit must not be set.
0RO 0bCoreReserved for Attention Button Pressed (ABP)
If an Attention Button is implemented, this bit is set when the
attention button is pressed. If an Attention Button is not
supported, this bit must not be set.
Table 66. SLOTSTS - Slot Status Register (Sheet 2 of 2)
Bit Access
Default
Value
RST/
PWR
Description