Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 133
Processor Configuration Registers
6.2.48 PEGLC - PCI Express-G Legacy Control
B/D/F/Type: 0/6/0/PCI
Address Offset: EC-EFh
Default Value: 00000000h
Access: RO; RW
Size: 32 bits
Controls functionality that is needed by Legacy (non-PCI Express aware) OS's during
run time.
0RO 0bCore
Current De-emphasis Level (CURDELVL):
Current De-emphasis Level –
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s speed, this bit is
0b.
Table 70. LSTS2 - Link Status 2 Register (Sheet 2 of 2)
Table 71. PEGLC - PCI Express-G Legacy Control Register
Bit Access Default
Value
RST/
PWR
Description
31:3 RO 00000000h Core Reserved
2RW 0b CorePME GPE Enable (PMEGPE)
0 = Do not generate GPE PME message when PME is received.
1 = Generate a GPE PME message when PME is received. This
enables the processor to support PMEs on the PEG port
under legacy OSs.
1RW 0b CoreHot-Plug GPE Enable (HPGPE)
0 = Do not generate GPE Hot-Plug message when Hot-Plug
event is received.
1 = Generate a GPE Hot-Plug message when Hot-Plug Event is
received. This enables the processor to support Hot-Plug
on the PEG port under legacy OSs
0RW 0b CoreGeneral Message GPE Enable (GENGPE)
0 = Do not forward received GPE assert/deassert messages.
1 = Forward received GPE assert/deassert messages.