Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 135
Processor Configuration Registers
Size: 32 bits
Describes the configuration of PCI Express Virtual Channels associated with this port.
6.3.3 PVCCAP2 - Port VC Capability Register 2
B/D/F/Type: 0/6/0/MMR
Address Offset: 108-10Bh
Default Value:00000000h
Access: RO;
Size:32 bits
Describes the configuration of PCI Express Virtual Channels associated with this port.
Table 74. PVCCAP1 - Port VC Capability Register 1
Bit Access Default
Value
RST/
PWR
Description
31:12 RO 00000h Core
Reserved
11:10 RO 00b Core Reserved
Reserved for Port Arbitration Table Entry Size ():
9:8 RO 00b Core Reserved
Reserved for Reference Clock ():
7 RO 0b Core Reserved
6:4 RO 000b Core Low Priority Extended VC Count (LPEVCC):
Indicates the number of (extended) Virtual Channels in
addition to the default VC belonging to the low-priority VC
(LPVC) group that has the lowest priority with respect to
other VC resources in a strict-priority VC Arbitration. The
value of 0 in this field implies strict VC arbitration.
3RO 0bCoreReserved
2:0 RO 000b Core Extended VC Count (EVCC):
Indicates the number of (extended) Virtual Channels in
addition to the default VC supported by the device.