Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
136 Document Number: 323178-003
6.3.4PVCCTL - Port VC Control
B/D/F/Type:0/6/0/MMR
Address Offset:10C-10Dh
Default Value:0000h
Access: RO; RW;
Size:16 bits
6.3.5VC0RCAP - VC0 Resource Capability
B/D/F/Type:0/6/0/MMR
Address Offset:110-113h
Default Value:00000001h
Access: RO;
Size:32 bits
Table 75. PVCCAP2 - Port VC Capability Register 2
Bit Access
Default
Value
RST/PWR Description
31:24 RO 00h Core VC Arbitration Table Offset (VCATO):
Indicates the location of the VC Arbitration Table. This
field contains the zero-based offset of the table in
DQWORDS (16 bytes) from the base address of the
Virtual Channel Capability Structure. A value of 0
indicates that the table is not present (due to fixed VC
priority).
23:8 RO 0000h Core Reserved
7:0 RO 00h Core Reserved for VC Arbitration Capability (VCAC)
Table 76. PVCCTL - Port VC Control
Bit Access
Default
Value
RST/PWR Description
15:4 RO 000h Core Reserved
3:1 RW 000b Core VC Arbitration Select (VCAS)
This field is programmed by software to the only possible
value as indicated in the VC Arbitration Capability field.
Since there is no other VC supported than the default,
this field is reserved.
0RO 0bCoreReserved for Load VC Arbitration Table
Used for software to update the VC Arbitration Table when
VC arbitration uses the VC Arbitration Table. As a VC
Arbitration Table is never used by this component this
field will never be used.
Table 77. VC0RCAP - VC0 Resource Capability (Sheet 1 of 2)
Bit Access
Default
Value
RST/PWR Description
31:24 RO 00h Core Reserved for Port Arbitration Table Offset
23 RO 0b Core Reserved