Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
138 Document Number: 323178-003
6.3.7 VC0RSTS - VC0 Resource Status
B/D/F/Type: 0/6/0/MMR
Address Offset: 11A-11Bh
Default Value: 0002h
Access: RO;
Size: 16 bits
Reports the Virtual Channel specific status.
Table 78. VC0RCTL - VC0 Resource Control
Bit Access
Default
Value
RST/PWR Description
31 RO 1b Core VC0 Enable (VC0E):
For VC0 this is hard wired to 1 and read only as VC0 can
never be disabled.
30:27 RO 0h Core Reserved
26:24 RO 000b Core VC0 ID (VC0ID):
Assigns a VC ID to the VC resource. For VC0 this is hard
wired to 0 and read only.
23:20 RO 0h Core Reserved
19:17 RW 000b Core Port Arbitration Select (PAS):
Port Arbitration Select – This field configures the VC
resource to provide a particular Port Arbitration service.
This field is valid for RCRBs, Root Ports that support peer
to peer traffic, and Switch Ports, but not for PCI Express
Endpoint devices or Root Ports that do not support peer to
peer traffic. The permissible value of this field is a number
corresponding to one of the asserted bits in the Port
Arbitration Capability field of the VC resource.
16 RO 0b Core Reserved
Reserved for Load Port Arbitration Table ():
15:8 RO 00h Core Reserved
7:1 RW 7Fh Core TC/VC0 Map (TCVC0M):
Indicates the TCs (Traffic Classes) that are mapped to the
VC resource. Bit locations within this field correspond to
TC values. For example, when bit 7 is set in this field, TC7
is mapped to this VC resource. When more than one bit in
this field is set, it indicates that multiple TCs are mapped
to the VC resource. In order to remove one or more TCs
from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the
TC labels are targeted at the given Link.
0RO 1bCoreTC0/VC0 Map (TC0VC0M):
Traffic Class 0 is always routed to VC0.