Datasheet

Processor Ball and Signal Information
323178-003 28
Figure 5. Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series Ballmap
(Top View, Upper-Left Quadrant)
71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36
BV
DC_TES
T_BV71
DC_TES
T_BV69
DC_TES
T_BV68
VSS VSS
SB_DQS
[6]
SB_DQ[4
8]
SB_DQ[4
7]
SB_DM[5
]
SB_DQS
#[5]
SB_DQ[3
9]
SB_DQ[3
7]
SB_DQ[3
4]
SB_DQ[3
3]
SB_DM[4
]
SB_ODT
[0]
SB_BS[1
]
SB_BS[0
]
SM_RCO
MP[2]
SB_CK[1
]
SA_MA[2
]
BU
SB_DM[6
]
SB_DQS
#[6]
VSS
SB_DQ[4
6]
VSS
SB_DQS
[5]
VSS
SB_DQ[4
1]
VSS
SB_ODT
[1]
VSS
SB_CAS
#
VSS
SB_MA[1
0]
SA_DQ[6
6]
SB_CK#[
1]
VSS
BT
DC_TES
T_BT71
DC_TES
T_BT69
VSS
SB_DQ[5
3]
SB_DQ[4
2]
SB_DQ[4
3]
SB_DQ[4
4]
SB_DQ[3
8]
SB_DQS
[4]
SB_DQS
#[4]
SB_DQ[3
2]
SB_DQ[3
6]
SB_MA[1
3]
SB_CS#[
1]
SB_WE#
SB_RAS
#
SA_BS[0]
SA_MA[0
]
BR
DC_TES
T_BR71
VSS VSS
SB_DQ[5
0]
SB_DQ[5
1]
SB_DQ[5
2]
BP
SB_DQ[4
9]
SA_DQS
#[6]
SB_DQ[4
5]
SB_DQ[4
0]
SB_DQ[3
5]
SB_CS#[
0]
VSS
SM_RCO
MP[1]
BN
VSS
SB_DQ[5
4]
SA_DQ[5
0]
VSS
SA_DM[6
]
SA_DQ[4
9]
SA_DQ[4
7]
SA_DQ[4
1]
SA_DQ[4
0]
SA_DQ[3
9]
SA_DQ[3
8]
SA_DQ[3
6]
SB_DQ[6
8]
BM
VSS
SA_DQS[
6]
SA_DQ[4
6]
VSS VSS
SA_DQ[3
3]
BL
VSS
SB_DQ[5
5]
VSS VSS VSS
SA_ODT[
1]
VSS
SA_RAS
#
BK
SB_DQ[6
0]
SB_DQ[6
1]
SA_DQ[5
4]
VSS
SA_DQ[5
5]
VSS VSS
SA_DQS
#[5]
SA_DQS[
4]
SA_CAS
#
SA_CK#[
1]
BJ
SB_DQ[5
6]
SB_DQS
[7]
SA_DQ[6
0]
VSS
SA_DQ[5
6]
SA_DQ[5
1]
SA_DQ[5
3]
SA_DQ[4
3]
SA_DQ[4
5]
SA_CS#[
1]
SA_DQ[3
2]
SA_DQ[7
1]
BH
VSS
SA_DM[7
]
VSS VSS
SA_DQ[4
2]
SA_DQS[
5]
SA_DQ[4
4]
VSS
SA_DQS
#[4]
SA_DQ[3
7]
SA_CS#[
0]
SA_BS[1]
SA_CK[1
]
BG
SB_DQ[5
8]
SB_DQS
#[7]
SA_DM[5
]
VSS
SA_DM[4
]
SA_DQ[7
0]
VSS
BF
SB_DQ[5
7]
SB_DM[7
]
SA_DQ[6
1]
SA_DQ[5
7]
VSS VTT0 VTT0
SA_DQ[5
2]
SA_DQ[4
8]
SA_DQ[3
5]
SA_DQ[3
4]
SA_ODT[
0]
SA_MA[1
3]
SA_WE#
BE
RSVD VSS RSVD VSS
SA_DQS[
7]
SA_DQS
#[7]
BD
SB_DQ[6
2]
SB_DQ[6
3]
VTT 0 VT T0 VSS VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1
BC
SA_DQ[6
3]
SB_DQ[5
9]
BB
VSS RSVD
SA_DQ[5
9]
SA_DQ[5
8]
VSS VT T0 VT T0 VSS VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1
BA
VSS
AY
VSS RSVD VSS
SA_DQ[6
2]
VSS VT T0 VSS VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1 VSS
AW
RSVD VSS VSS VT T0 VSS VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1 VSS
AV
RSVD RSVD
PM_EXT
_TS#[0]
PM_EXT
_TS#[1]
AU
RSVD VSS RSVD VSS VT T0 VT T0 VSS VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1
AT
RSVD RSVD VSS
AR
RSVD RSVD VSS VT T0 VT T0 VSS VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1
AP
VSS RSVD VSS
AN
GFX_VID
[4]
RSVD VSS VT T0 VT T0 VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1 VSS
AM
GFX_VID
[6]
GFX_VID
[5]
RSVD VSS
AL
GFX_DP
RSLPVR
GFX_IM
ON
VSS VT T0 VT T0 VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1 VSS
AK
RSVD VSS RSVD RSVD VSS VCAP2 VCAP2 VCAP2 VCAP0 VSS VCAP0 VSS VCAP0 VSS VCAP1 VSS VCAP1 VSS VCAP1 VSS
AJ
VSS
AH
GFX_VID
[3]
GFX_VR
_EN
RSVD VSS VCAP2 VCAP2 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AG
GFX_VID
[2]
GFX_VID
[1]
VSS
AF
GFX_VID
[0]
VSS VSS VCAP2 VCAP2 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VTT 0 VT T0
AE
VSS COMP0 VSS
AD
COMP3 COMP1 VSS VCAP2 VCAP2 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VT T0 VT T 0
AC
RSVD COMP2 RSVD VSS VSS
AB
VSS VSS VCAP2 VCAP2 VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VSS