Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
72 Document Number: 323178-003
6.1.1 DEVEN - Device Enable
B/D/F/Type: 0/0/0/PCI
Address Offset: 54-57h
Default Value: 0000010Bh
Access: RW-L; RO; RW
Size: 32 bits
BIOS Optimal Default 000000h
Allows for enabling/disabling of PCI devices and functions that are within the processor.
The table below the bit definitions describes the behavior of all combinations of
transactions to devices controlled by this register. All the bits in this register are Intel
TXT Lockable.
Table 15. DEVEN - Device Enable Register
Bit Access
Default
Value
RST/
PWR
Description
31:15 RO 0h Reserved
14 RW-L 0b Core Reserved
13 RW-L 0b Core PEG1 Enable (D6EN)
0 = Bus 0 Device 6 Function 0 is disabled
and hidden.
1 = Bus 0 Device 6 Function 0 is enabled
and visible.
12:12 RO 0h Reserved
11 RW-L 0b Core Reserved
10 RW-L 0b Core Reserved
9:9 RO 0h Reserved
8RW-L 1b CoreReserved
7:4 RO 0h Reserved
3RW-L 1b CoreInternal Graphics Engine Function 0
(D2F0EN)
0 = Bus 0 Device 2 Function 0 is disabled
and hidden
1 = Bus 0 Device 2 Function 0 is enabled
and visible
2:2 RO 0h Reserved
1RW-L 1b CorePCI Express Port (D1EN)
0 = Bus 0 Device 1 Function 0 is disabled
and hidden.
1 = Bus 0 Device 1 Function 0 is enabled
and visible.
0RO 1bCoreHost Bridge (D0EN)
Bus 0 Device 0 Function 0 may not be
disabled and is therefore hard wired to 1.