Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 73
Processor Configuration Registers
6.1.2 ERRSTS - Error Status
B/D/F/Type: 0/0/0/PCI
Address Offset: C8-C9h
Default Value: 0000h
Access: RO; RW1C-S;
Size: 16 bits
This register is used to report various error conditions via the SERR DMI messaging
mechanism. An SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a '1' to it
.
Table 16. Error Status Register (Sheet 1 of 2)
Bit Access Default
Value
RST/
PWR
Description
15:13 RO 000b Core Reserved
12 RW1C-S 0b Core Processor Software Generated Event for
SMI (GSGESMI):
This indicates the source of the SMI was a
Device 2 Software Event.
11 RW1C-S 0b Core Processor Thermal Sensor Event for SMI/
SCI/SERR (GTSE):
Indicates that a Processor Thermal Sensor trip
has occurred and an SMI, SCI or SERR has
been generated. The status bit is set only if a
message is sent based on thermal event
enables in Error command, SMI command and
SCI command registers. A trip point can
generate one of SMI, SCI, or SERR interrupts
(two or more per event is illegal). Multiple trip
points can generate the same interrupt, if
software chooses this mode, subsequent trips
may be lost. If this bit is already set, then an
interrupt message will not be sent on a new
thermal sensor event
10 RO 0b Core Reserved
9RW1C-S 0b CoreLOCK to non-DRAM Memory Flag (LCKF):
When this bit is set to 1, the Processor has
detected a lock operation to memory space that
did not map into DRAM
8RO 0b CoreReserved
7RW1C-S 0b CoreDRAM Throttle Flag (DTF):
1: Indicates that a DRAM Throttling
condition occurred.
0: Software has cleared this flag since the
most recent throttling event.
6:2 RO 00h Core
Reserved