Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 75
Processor Configuration Registers
Table 17. Error Command Registers
Bit Access Default
Value
RST/
PWR
Description
15:12 RO 000b Core Reserved
11 RW 0b Core SERR on Processor Thermal Sensor Event
(TSESERR):
1: The Processor generates a DMI SERR special
cycle when bit 11 of the ERRSTS is set. The
SERR must not be enabled at the same time as
the SMI for the same thermal sensor event.
0: Reporting of this condition via SERR
messaging is disabled.
10 RO 0b Core Reserved
9RW 0b CoreSERR on LOCK to non-DRAM Memory
(LCKERR):
1: The Processor will generate a DMI SERR
special cycle whenever a CPU lock cycle is
detected that does not hit DRAM.
0: Reporting of this condition via SERR
messaging is disabled
8RW 0b CoreReserved
7RW 0b Core
SERR on DRAM Throttle Condition (ERR):
0 = Reporting of this condition via SERR
messaging is disabled.
1 = The memory controller generates a DMI
SERR special cycle when a DRAM Read or Write
Throttle condition occurs.
6:2 RO 00h Core
Reserved
1RW 0b CoreSERR Multiple-Bit DRAM ECC Error
(DMERR):
1: The Processor generates an SERR message
over DMI when it detects a multiple-bit error
reported by the DRAM controller.
0: Reporting of this condition via SERR
messaging is disabled.
For systems not supporting ECC this bit must
be disabled.
0RW 0b CoreSERR on Single-bit ECC Error (DSERR):
1: The Processor generates an SERR special
cycle over DMI when the DRAM controller
detects a single bit error.
0: Reporting of this condition via SERR
messaging is disabled.
For systems that do not support ECC this bit
must be disabled.