Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 77
Processor Configuration Registers
6.1.5 C0WRDATACTRL - Channel 0 Write Data Control
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 24D-24Fh
Default Value: 004111h
Access: RW
Size: 24 bits
BIOS Optimal Default 00h
Table 19. Channel 0 Write Data Control Registers
Bit Access
Default
Value
RST/
PWR
Description
23:16 RW 00h Core ECC bit invert vector (C0sd_cr_eccbitinv):
This vector operates individually for every ECC
bit in the selected 64b ECC block, during write
to DRAM. For all k between 0 and 7, when
bit(k) is set to 1, the value for the k ECC bit
(which corresponds with k data byte lane) is
inverted. Otherwise, the value for the k ECC bit
is not affected.
15 RW 0b Core ECC Diagnostic Enable
(C0sd_cr_eccdiagen):
1: The ECC bit invert vector is used to invert
selected ECC bits, during writes to DRAM.
0: The diagnostic feature is turned off.
14:0 RW 4110h Core Reserved