Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 91
Processor Configuration Registers
6.2.7 CL6 - Cache Line Size
B/D/F/Type: 0/6/0/PCI
Address Offset: Ch
Default Value: 00h
Access: RW
Size: 8 bits
6.2.8 HDR6 - Header Type
B/D/F/Type: 0/6/0/PCI
Address Offset: Eh
Default Value: 01h
Access: RO
Size: 8 bits
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Regost
Table 30. CL6 - Cache Line Size Register
Bit Access
Default
Value
RST/
PWR
Description
7:0 RW 00h Core Cache Line Size (Scratch pad)
Implemented by PCI Express devices as a read-write field for
legacy compatibility purposes but has no impact on any PCI
Express device functionality.
Table 31. HDR6 - Header Type Register
Bit Access Default
Value
RST/
PWR
Description
7:0 RO 01h Core Header Type Register (HDR)
Returns 01 to indicate that this is a single function device with
bridge header layout.