Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
92 Document Number: 323178-003
6.2.9 PBUSN6 - Primary Bus Number
B/D/F/Type: 0/6/0/PCI
Address Offset: 18h
Default Value: 00h
Access: RO
Size: 8 bits
This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI
Bus 0.
6.2.10 SBUSN6 - Secondary Bus Number
B/D/F/Type: 0/6/0/PCI
Address Offset: 19h
Default Value: 00h
Access: RW
Size: 8 bits
This register identifies the bus number assigned to the second bus side of the “virtual”
bridge, i.e., to PCI Express-G. This number is programmed by the PCI configuration
software to allow mapping of configuration cycles to PCI Express-G.
Table 32. PBUSN6 - Primary Bus Number Register
Bit Access Default
Value
RST/
PWR
Description
7:0 RO 00h Core Primary Bus Number (BUSN)
Configuration software typically programs this field with the
number of the bus on the primary side of the bridge. Since
Device 6 is an internal device and its primary bus is always 0,
these bits are read only and are hard wired to 0.
Table 33. SBUSN6 - Secondary Bus Number Register
Bit Access Default
Value
RST/
PWR
Description
7:0 RW 00h Core Secondary Bus Number (BUSN)
This field is programmed by configuration software with the bus
number assigned to PCI Express-G.