Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 93
Processor Configuration Registers
6.2.11 SUBUSN6 - Subordinate Bus Number
B/D/F/Type: 0/6/0/PCI
Address Offset: 1Ah
Default Value: 00h
Access: RW
Size: 8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI
Express-G. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express-G.
6.2.12 IOBASE6 - I/O Base Address
B/D/F/Type: 0/6/0/PCI
Address Offset: 1Ch
Default Value: F0h
Access: RO; RW
Size: 8 bits
This register controls the CPU to PCI Express-G I/O access routing based on the
following formula:
IO_BASE=< address =<IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range is aligned
to a 4-KB boundary.
Table 34. SUBUSN6 - Subordinate Bus Number Register
Bit Access
Default
Value
RST/
PWR
Description
7:0 RW 00h Core Subordinate Bus Number (BUSN)
This register is programmed by configuration software with the
number of the highest subordinate bus that lies behind the Device
6 bridge. When only a single PCI device resides on the PCI
Express-G segment, this register will contain the same value as
the SBUSN6 register.