Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
94 Document Number: 323178-003
6.2.13 IOLIMIT6 - I/O Limit Address
B/D/F/Type: 0/6/0/PCI
Address Offset: 1Dh
Default Value: 00h
Access: RO; RW
Size: 8 bits
This register controls the CPU to PCI Express-G I/O access routing based on the
following formula:
IO_BASE=< address =<IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range is at
the top of a 4-KB aligned address block.
Table 35. IOBASE6 - I/O Base Address Register
Bit Access Default
Value
RST/
PWR
Description
7:4 RW Fh Core I/O Address Base (IOBASE)
Corresponds to A[15:12] of the I/O addresses passed by bridge 1
to PCI Express-G.
BIOS must not set this register to 00h otherwise 0CF8h/0CFCh
accesses is forwarded to the PCI Express hierarchy associated
with this device.
3:0 RO 0h Core Reserved
Table 36. IOLIMIT6 - I/O Limit Address Register
Bit Access
Default
Value
RST/
PWR
Description
7:4 RW 0h Core I/O Address Limit (IOLIMIT)
Corresponds to A[15:12] of the I/O address limit of Device 6.
Devices between this upper limit and IOBASE6 is passed to the
PCI Express hierarchy associated with this device.
3:0 RO 0h Core Reserved