Datasheet

Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
August 2010 Datasheet Addendum
Document Number: 323178-003 95
Processor Configuration Registers
6.2.14 SSTS6 - Secondary Status
B/D/F/Type: 0/6/0/PCI
Address Offset: 1E-1Fh
Default Value: 0000h
Access: RWC; RO
Size: 16 bits
SSTS6 is a 16-bit status register that reports the occurrence of error conditions
associated with secondary side (i.e., PCI Express-G side) of the “virtual” PCI-to-PCI
bridge embedded within processor.
Table 37. SSTS6 - Secondary Status Register
Bit Access Default
Value
RST/
PWR
Description
15 RWC 0b Core Detected Parity Error (DPE)
This bit is set by the Secondary Side for a Type 1 Configuration
Space header device whenever it receives a Poisoned TLP,
regardless of the state of the Parity Error Response Enable bit in
the Bridge Control Register.
14 RWC 0b Core Received System Error (RSE)
This bit is set when the Secondary Side for a Type 1 configuration
space header device receives an ERR_FATAL or ERR_NONFATAL.
13 RWC 0b Core Received Master Abort (RMA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Unsupported Request
Completion Status.
12 RWC 0b Core Received Target Abort (RTA)
This bit is set when the Secondary Side for Type 1 Configuration
Space Header Device (for requests initiated by the Type 1 Header
Device itself) receives a Completion with Completer Abort
Completion Status.
11 RO 0b Core Signaled Target Abort (STA)
Not Applicable or Implemented. Hard wired to 0. The processor
does not generate Target Aborts (the processor will never
complete a request using the Completer Abort Completion
status).
10:9 RO 00b Core DEVSELB Timing (DEVT)
Not Applicable or Implemented. Hard wired to 0.
8RWC 0b CoreMaster Data Parity Error (SMDPE)
When set indicates that the PROCESSOR received across the link
(upstream) a Read Data Completion Poisoned TLP (EP=1). This
bit can only be set when the Parity Error Enable bit in the Bridge
Control register is set.
7RO 0bCoreFast Back-to-Back (FB2B)
Not Applicable or Implemented. Hard wired to 0.
6RO 0bCoreReserved
5RO 0bCore66-/60-MHz Capability (CAP66)
Not Applicable or Implemented. Hard wired to 0.
4:0 RO 00h Core Reserved