Datasheet

Processor Configuration Registers
Intel
®
Core
TM
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
®
Celeron
®
Processor P4505, U3405 Series
Datasheet Addendum August 2010
96 Document Number: 323178-003
6.2.15 MBASE6 - Memory Base Address
B/D/F/Type: 0/6/0/PCI
Address Offset: 20-21h
Default Value: FFF0h
Access: RO; RW
Size: 16 bits
This register controls the CPU to PCI Express-G non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-
only and return zeroes when read. This register must be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range is aligned to a 1-MB boundary.
Table 38. MBASE6 - Memory Base Address Register
Bit Access Default
Value
RST/
PWR
Description
15:4 RW FFFh Core Memory Address Base (MBASE)
Corresponds to A[31:20] of the lower limit of the memory
range that is passed to PCI Express-G.
3:0 RO 0h Core Reserved