Intel Celeron D Processor 300 Sequence

Summary Tables of Changes
10 Specification Update
Steppings
Number
B1 C1 D0
Plans ERRATA
AD1 X X X No Fix Memory Aliasing of Pages as Uncacheable Memory Type and Write Back (WB) May
Hang the System
AD2 X X X No Fix Data Breakpoints on the High Half of a Floating Point Line Split may not
be Captured
AD3 X X X No Fix Incorrect Access Controls to MSR_LASTBRANCH_0_FROM_LIP MSR
Registers
AD4 X X X No Fix FXRSTOR May Not Restore Non-canonical Effective Addresses on
Processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Enabled
AD5 X X X No Fix FXRSTOR May Not Restore Non-canonical Effective Addresses on
Processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Enabled
AD6 X X X No Fix A Push of ESP that Faults may Zero the Upper 32 Bits of RSP
AD7 X X X No Fix Checking of Page Table Base Address May Not Match the Address Bit
Width Supported by the Platform
AD8 X X X No Fix With TF (Trap Flag) Asserted, FP Instruction That Triggers an Unmasked
FP Exception May Take Single Step Trap Before Retirement of
Instruction
AD9 X X X No Fix BTS(Branch Trace Store) and PEBS(Precise Event Based Sampling) May
Update Memory outside the BTS/PEBS Buffer
AD10 X X X No Fix Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS
Instruction with Fast Strings Enabled
AD11 X X X No Fix REP STOS/MOVS Instructions with RCX >=2^32 May Cause a System
Hang
AD12 X X X No Fix A 64-Bit Value of Linear Instruction Pointer (LIP) May be Reported
Incorrectly in the Branch Trace Store (BTS) Memory Record or in the
Precise Event Based Sampling (PEBS) Memory Record
AD13 X X X No Fix Two Correctable L2 Cache Errors in Close Proximity May Cause a System
Hang
AD14 X X X No Fix Processor May Hang with a 25% or Less STPCLK# Duty Cycle
AD15 X X X No Fix Machine Check Exceptions May not Update Last-Exception Record MSRs
(LERs)
AD16 X X X No Fix Writing the Local Vector Table (LVT) when an Interrupt is Pending May
Cause an Unexpected Interrupt
AD17 X X X No Fix At a Bus Ratio of 13:1, RCNT and Address Parity May be Incorrect
AD18 X X X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment
Check Exception
AD19 X X X No Fix L2 Cache ECC Machine Check Errors May be erroneously Reported after
an Asynchronous RESET# Assertion