Intel Celeron D Processor 300 Sequence

Summary Tables of Changes
Specification Update 11
Steppings
AD20 X X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect
Address Translations
AD21 X X X No Fix Writing Shared Unaligned Data that Crosses a Cache Line without Proper
Semaphores or Barriers May Expose a Memory Ordering Issue
AD22 X X X No Fix The IA32_MC0_STATUS and IA32_MC1_STATUS Overflow Bit is not set
when Multiple Un-correctable Machine Check Errors Occur at the Same
Time
AD23 X X X No Fix Processor May Fault When the Upper 8 Bytes of Segment Selector Is
Loaded from a Far Jump through a Call Gate via the Local Descriptor
Table
AD24 X X X No Fix The Processor May Issue Front Side Bus Transactions up to 6 Clocks
after RESET# is Asserted
AD25 X X X No Fix Front Side Bus Machine Checks May be Reported as a Result of On-
Going Transactions during Warm Reset
AD26 X X X No Fix A VM Exit Occuring in IA-32e Mode May Not Produce a VMX Abort When
Expected
Number SPECIFICATION CHANGES
AD1 VTT_SEL Signal Specification change
Number SPECIFICATION CLARIFICATIONS
There are no Specification Clarifications in this Specification Update revision.
Number DOCUMENTATION CHANGES
There are no Documentation Changes in this Specification Update revision.
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